1. Field of the Invention
This invention relates to a check system for detecting malfunction of an error detection circuit.
2. Description of the Prior Art
In data transfer inside a computer, or a data transmission between input/output units, there are some occasions when an unnecessary bit is picked or a necessary bit is omitted on account of external noise, a decrease in the output from an amplifier used, or the like.
To avoid this, there has been provided an error detection circuit in a data processing circuit at a place where an error is likely to occur, for example, in a buffer register which achieves data transfer between it and a memory, or in a buffer register which performs data transfer between it and a logical operation circuit or an input/output unit. With speeding up or complication of equipment, however, it is considered quite possible that the error detection circuit itself may make an error in some cases.
In some of the counters, registers or the like which operate in synchronism with clock pulses, a change in the number of 1, that is, a parity change, can be predicted from the state before one cycle period (1t) has passed. In such a case, it is possible to check malfunction of the error detection circuit itself by using the predicted value, but in the case where the 1 t period is short, a logic circuit for checking the operation of the error detection circuit must be formed with high-speed elements. Further, it may also be necessary to employ clock pulses for the timing of the check in some cases.